Non-volatile semiconductor memory cells permitting charge storage capability are well known in the art. The charges stored thereon define the states of a memory cell. Typically, the states can be either two levels or more than two levels (for multi-level states storage). In terms of charge storage scheme, in general, the memory cells can be divided into two main categories. The first type of memory uses a conductive or semiconductor region as the storage site. The storage site is electrically insulated from but capacitively coupled to surrounding electrodes through a storage insulator. Charges stored in such memory are evenly distributed through out the conductive region. Memory cells with such type of charge storage scheme are commonly referred as “floating-gate” type of cells. Typically, such floating gate memory cells have been of the single-gate type, split-gate type, or stack-gate type, or a combination thereof.
The second type of memory stores charges in a plurality of discrete storage sites, such as trapping centers of an appropriate dielectric material (“trapping dielectric”). The storage sites in the trapping dielectric is electrically insulated from but capacitively coupled to surrounding electrodes through a storage insulator. The Memory cells employing such type of storage scheme are commonly referred as “charge-trapping” memory cells. The storage sites can be also in nano-crystal form, and the memory cells employing such type of storage scheme are commonly referred as “nano-crystal” memory cells. These memory cells do not require a floating-gate. Therefore, it provides advantages over the floating-gate memory cells in area such as negligible interference between adjacent cells, and reduced process complexity. Furthermore, the charges in such memory cell can be stored at localized sites (traps or nano-crystals). Therefore it also has the advantage that in the event there is a local breakdown in the storage dielectric or in surrounding dielectrics, charges stored at other sites can still be retained.
Single-gate memory has the advantages over other types of memory cells on a simpler process in manufacturing such type of memory cell. This type of memory can potentially be manufactured in process as simple as a conventional CMOS, thus can be manufactured with low cost and can be easily embedded in CMOS logic products. Such non-volatile memory cell has been proposed in U.S. published application Ser. Nos. 2004/0109364 A1, 2004/0109380 A1, in U.S. Pat. No. 6,617,637, and in U.S. published application Ser. No. 2004/0061168 A1, which are hereby incorporated by reference. As will be described hereinafter, there are several disadvantages in the disclosures of prior arts. The present invention provides cell structures and operation method with advantages over the prior arts.
The present invention can best be understood with an understanding of how the memory cells in prior arts are constructed and how they are operated for program and erase operations. Thus a short introduction is presented to describe the prior art cell structure, and the cell operations.
U.S. published application Ser. Nos. 2004/0109364 A1 and 2004/0109380 A1 taught memory cell structure and operation method (e.g. program and erase). Illustrated in FIG. 1 is a cross sectional view for cell structure 100 of the prior art. The cell 100 comprises a first and a second p-type metal-oxide semiconductor field-effect-transistors (p-FETs 10 and 12) formed in an n-type of Well 14 (n-Well). Both p-FETs 10 and 12 are connected in series by a shared region 16 with the gate of the first p-FET 10 functioning as a select gate (SG 18), and gate of the second p-FET 12 functioning as a floating-gate (FG 20) for storing charge carriers. A source region 22 of the first p-FET is connected to a source-line with a source-line voltage 24 applied thereto. Similarly, a drain region 26 of the second p-FET is connected to a bit-line with a bit-line voltage 28 applied thereto. The SG 18 of the memory cell 100 is connected to a select-gate voltage 30 of appropriate voltages during cell operations. The cells are electrically programmed by heating up channel holes 32 through which impacted channel hot electrons 34 (ICHE) are created and injected into the floating gate 20. For re-programmability, the cell need be erased by application of ultraviolet 36 (UV) light treatment. Therefore, the cells are used in devices typically known as EPROM devices well-known in the art. During cell operation (e.g. program and read), the n-Well 14 is biased at a voltage different than ground voltage. Therefore, though not shown in the prior art, the n-Well 14 need be formed in a p-type Well or a p-type substrate. Such type of memory cells can be manufactured in a conventional CMOS process having an n-Well in a p-type semiconductor substrate (Sub). However, erasing such cells requires erasure of the entire memory device by application of UV light even erase is made for changing the content of only a single byte. The memory device has to be removed from the circuit board in order to perform UV treatment for the erase operation. The process is tedious and adds inconvenience in product applications.
U.S. Pat. No. 6,617,637 taught an electrically erasable and programmable memory (EEPROM) cell structure and operation method, and is hereby incorporated by reference. The cell comprises a structure similar to the one in FIG. 1 except that the drain next to the floating gate comprises a heavily doped n-type region (n+ region) formed in a lightly doped p-type region (p− region). The cell is programmed by injecting ICHE into floating gate and erased by Band-to-Band-Tunneling (BTBT) injection of holes into the floating gate. The cell structure and operation method require the p− region having a metallurgical junction depth deeper than that of the n+ region and yet shallower than that of the n-Well, in order to isolate the n+ region from the n-Well. The needs on a shallower p− region (or equivalently a deeper n-Well region) prohibit this memory cell from being implemented in the conventional CMOS process, as neither of these regions is available in the base-line process of conventional CMOS.
U.S. Pat. No. 5,736,764 taught an electrically erasable and programmable memory (EEPROM) cell structure and operation method, and is hereby incorporated by reference. The cell comprises a p-FET-based cell structure similar to the one in FIG. 1 except that a control gate is added in the cell structure for operating the cell. The cell is programmed by injecting ICHE onto floating gate and erased by removing electrons from floating gate through Fowler-Nordheim tunneling mechanism. The control gate is essential for the cell operation and comprises a p-type diffusion layer. The memory cell is electrical erasable and thus has the advantage over cells in U.S. application Ser. Nos. 2004/0109364 A1 and 2004/0109380 A1. However, the p-type diffusion layer has to be disposed under a portion of the floating gate in order to effectively perform the control gate function. Such kind of p-type diffusion is unavailable in the conventional CMOS process, thus the cell structure cannot be realized in the conventional CMOS. Further, the control gate occupies a large portion of the cell area thus unavoidably enlarges the cell size.
U.S. published application Ser. No. 2004/0061168 A1 taught an electrically erasable and programmable memory (EEPROM) cell structure 200 and operation method. The cell is illustrated in n-FET based architecture, and is programmed by substrate hot electron injection (SHEI) and erased by Fowler-Nordheim tunneling. The cell structure comprises a floating gate, and two separated p-Wells with a first p-Well having a pair of n-type FETs (n-FETs) connected in series and a second p-Well having an n-FET. Illustrated in FIGS. 2A and 2B (prior art) are cross sectional view of a cut-plane along line BB in FIG. 3a of the prior art for the program and the erase operations, respectively. Referring to FIG. 2A, the floating gate 40 is disposed over and insulated from the first p-Well 42 and the second p-Wells 44 by an insulator 46. A n+ region 48 formed in the second p-Well 44 functions as a control gate of the memory cell 200 to allow charge carriers be added onto or removed from the portion of floating gate 40 that is disposed over the first p-Well 42. The bias condition shown in FIG. 2A permit substrate electrons 49 be heated up to transport through the n-channel layer 50 and be injected into the floating gate 40 along a trajectory 51 to perform a program operation on the memory cell. FIG. 2B is a similar cross sectional view as in FIG. 2A except bias condition is set for the erase operation. A voltage in the range of about 10V is applied across the insulator 46 between floating gate 40 and the 1st p-Well 42 (−5V applied at the control gate 48 and the second p-Well 44, and +5 V applied to the 1st p-Well 42). The bias and the cell structure permits electrons 52 in FG 40 be removed along the trajectory 53 shown in dash line. Notably, to support erase operation, both p-Wells are isolated from a p-substrate 54 by a deeper n-Well (deep n-Well 56) having a well depth deeper than the p-Wells 42 and 44 in order to avoid forward-biasing any p-Well during the erase operation of the cell 200. The memory cell 200 is electrical erasable and thus has the advantage over cells in U.S. application Ser. Nos. 2004/0109364 A1 and 2004/0109380 A1. However, the requirement on isolated p-Wells from the substrate prohibits this memory cell from being implemented in the conventional CMOS process, where the deep n-Well 56 is not available. Additionally, the requirement on a control gate 48 for operating the cell requires the second p-Well 44 be an isolation well (to isolate the control gate 48 from the deep n-Well 56). Therefore, it unavoidably enlarges the cell size. This issue is worse when a Well region is involved (due to the looser design rule for Well-to-Well spacing than other rules). It is noted that the memory cell can be configured to a p-FET based cell by replacing the n-FETs with p-FETs, and by proper changing the Well type to an opposite one. Specifically, in such case, the cell can comprise two n-Wells isolated by a deep p-Well in an n-type substrate. Nevertheless, the forgoing issues on larger cell size and on incompatibility with the conventional CMOS process remain be the main disadvantages of such cell.
As described hereinbefore, the memory cells in U.S. Pat. No. 5,736,764 and U.S. application Ser. No. 2004/0061168 A1 are erased by Fowler-Nordheim tunneling mechanism. Similar technique has been widely employed in other types of single-gate memory cells (for example, U.S. Pat. Nos. 5,604,700, and 5,465,231). In erasing these types of nonvolatile memories with such mechanism, a large voltage drop (typically ranging from 9 to 20V) across the storage insulator is required to perform the operation in order to set a desired logic states (e.g. a “0” state) to the memory. Employing Fowler-Nordheim tunneling mechanism to erase these types of memory cells unavoidably introduces stress field in the range of about 10 MV/cm to the storage insulator, which isolates the floating gate or the storage sites from surrounding conductive regions. This high field stress effect on the storage insulator results in charge leakage and retention failure even when memory cells are under a low field condition. This effect is known as the Stress Induced Leakage Current (SILC), and has been shown being the dominant leakage mechanism causing retention failure in non-volatile memory industry (see K. Naruke et al, “Stress Induced Leakage Current Limiting to Scale Down EEPROM Tunnel Oxide Thickness”, IEDM Technical Digest, pp. 424–427, 1988.). Therefore, the memory cell disclosed in U.S. published application Ser. No. 2004/0061168 A1 is believed suffered from high field induced SILC issue.
The present invention provides cell structure and operation method of a single poly electrical erasable programmable memory cell that can be fabricated in the conventional CMOS process. The erase operation of the present cell permits the voltage drop across the storage insulator be confined in range less than about 2 V. Therefore, it avoids the high field stress on the insulator and hence the SILC issue. Other advantages, objects and features of the present invention will become apparent by a review of the specification, claims and appended figures.